Moore's law has dictated for decades scaling of Si-based CMOS technology in terms of performance, power consumption, area, and cost. As we have reached the physical limits of scaling Si channels, however, alternative materials with higher intrinsic carrier mobilities such as Ge and III-V compound semiconductors are needed. It is anticipated that highly performing III-V or Ge based devices will be used only in those circuits of a Central Processing Unit (CPU) or analog/Radio Frequency (RF) front end chips where high speed is required, while their more conservative Si counterparts will still be used for all non-core peripheral functions, such as for Input/Output (I/O).
Therefore, a scheme allowing co-integration of Ge and III-V together with Si channels is desired. For the heterogeneous integration of III-V or Ge on Si substrates, one of the likely schemes possible for integration is the use of the aspect-ratio-trapping (ART) technique. In this approach, the III-V or Ge layer is selectively grown in high aspect ratio trenches of the Shallow Trench Isolation (STI) type. Selective epitaxial growth (SEG) or Selective Area Growth (SAG) of Ge or III-V material in narrow trenches between SiO2 isolation structures allows defects to be confined and trapped at the vertical interface between the growing epi-layer and the oxide. However, many issues remain in the manufacture of such Ge and III-V based devices. In particular, Ge or III-V based FinFET devices produced by ART have shown high levels of source to drain leakage (see N. Waldron et al., International SiGe Technology Device Meeting 2012, Berkeley). Also, the methods of manufacturing these devices are usually complicated and labour-intensive.